Workshop on FPGAs for scientific simulation and data analytics
NOTE: This workshop is by invitation only. Those who are interested in attending should contact
Kazutomo Yoshii at ky@anl.gov, including your experiences on FPGA in your e-mail message.
Date/Time: Jan. 21 (Thu.), 2016 9:00 - 17:15 (Central) for the main workshop
Jan. 22 (Fri.) for topic-based group discussion
Location: Argonne National Laboratory, Building 240 (the meeting room numbers will be sent via e-mail)
Directions to Argonne: http://www.anl.gov/directions-and-visitor-information
Workshop Motivation
The performance evolution of high-performance computing (HPC) and data analytic systems has been
governed in the past by integration improvements in the CMOS technology. This trend is expected to
continue until the mid-2020s when CMOS features will reach 5-7 nm. In the following period, performance
progress for CMOS-based integrated circuit devices will no longer come from higher levels of integration,
and other approaches will be needed.
The convergence of several technologies makes HPC-relevant FPGA-powered systems attractive.
These technologies are (1) new FPGA system-on-chip devices featuring multicore CPUs, FPGAs, and
thousands of hardened floating-point data signal processing blocks; (2) robust compiler technologies
capable of targeting heterogeneous systems; and (3) tools for transforming intermediate representation
objects into a hardware description language such as VHDL and Verilog, available from research groups
and from vendors. These, combined with the push toward expressing parallelism and data dependencies
specified by parallel programming APIs (e.g., OpenMP, OpenCL), open up FPGA-based solutions
for serious exploration in scientific simulations and data analytics.
Workshop Objectives
The workshop will pursue several objectives. First, it will establish the state of the art in this domain
internationally. Second, it will help understand trends in FPGA technologies and better identify and
understand open problems and challenges. Third, it will provide a unique opportunity to identify
and to discuss potential collaborations.
Workshop Organization
The workshop is organized to maximize interactions and discussions among participants. It will feature
talks from key players of FPGA and scientific simulation and data analytics domains. Considerable time
will be allotted during coffee breaks, lunch, dinner, and special sessions to discuss potential collaborations.
Agenda for the workshop on Jan. 21 (Thu.)
Talk abstracts are here.
| Time | Title | Presenter or Session chair |
|---|---|---|
| 9:00 - 9:10 | Opening and introduction | Franck Cappello, Argonne |
| 9:10 - 10:30 | Session: Architecture (1) | Chair: Franck Cappello, Argonne |
| Argonne interest in post-Moore research | Marc Snir, Argonne | |
| Argonne "Re-form" project | Kazutomo Yoshii, Hal Finkel, Argonne | |
Disruptive changes at the end of Moore’s law beyond exascale, and how FPGAs need to become more "data-centric" | Satoshi Matsuoka, Titech, Japan | |
| 10:30 - 11:00 | Break | |
| 11:00 - 12:00 | Session: Architecture (2) | Chair: Franck Cappello, Argonne |
| Inexact computing and FPGA | Krishna Palem, Rice University | |
| Creating an FPGA accelerator from scratch in 15 min! | Andreas Olofsson, Adapteva | |
| 12:00 - 14:30 | Session: Programming Model | Chair: Kazutomo Yoshii, Argonne |
| FPGA experience at Barcelona Supercomputer Center* | Carlos Alvarez, BSC, Spain | |
| Altera OpenCL | Greg Nash, Altera | |
| Xilinx FPGA and programming tools* | Ronan Keryell, Xilinx | |
| Lessons learned from HPRC | Volodymyr Kindratenko, NCSA | |
| 14:00 - 14:30 | Break | |
| 14:30 - 16:30 | Session: Compiler and performance analysis | Chair: Hal Finkel, Argonne |
| Autotuning FPGA design parameters for performance and power | Azamat Mametjanov | |
Communication and calculation co-design for HPC on FPGA | Taisuke Boku, University of Tsukuba, Japan | |
| High-level design flows - early planning | Seda Ogrenci-Memik, Northwestern University | |
| Towards understanding the performance of FPGAs using OpenCL benchmarks | Naoya Maruyama, Riken, Japan | |
| 16:30 | Panel: Gaps and mitigations for FPGA adoption in HPC | Moderator, Franck Cappello, Argonne |
| 17:15 | Wrap-up |
* temporary title
Agenda for the discussion meeting on Jan. 22 (Fri.)
Friday morning will focus on identifying collaboration topics and establishing collaborations between potential partners.
| Topic | ||
|---|---|---|
| 9:00 | Post-modern C++ abstractions for FPGA heterogeneous computing with OpenCL SYCL & SPIR-V | Ronan Keryell, Xilinx |
| 9:30 | Discussion on collaborations | |
| 10:30 | Break | |
| 10:45 | Applications, benchmarks, testbeds sharing | |
| 12:00 | Wrap-up |
Organizers
Kazutomo Yoshii Argonne National Laboratory
Franck Cappello Argonne National Laboratory
Hal Finkel Argonne National Laboratory
Fangfang Xia Argonne National Laboratory